NetLogic Microsystems announced a second-generation, 28-nanometer member of its Linux-ready XLP multicore processor family, claimed to be five to seven times faster. The XLP II integrates up to 80 NXCPUs (threads) via up to 20 2.5GHz MIPS64 cores, boasts 100Gbps network processing performance per processor,supports coherent clustering of up to eight processors, and achieves up to 800Gbps throughput, claims the company.

Like the the original eight-core XLP832 announced in 2009, the six-core XLP864 announced in April, and the quad-core XLP316 announced in May, the XLP II is aimed at various levels of LTE mobile infrastructure, data center, enterprise networking, storage, and security applications. The key difference here is the move from 40-nanometer (nm) fabrication to a 28nm TSMC process, which, among other benefits, enables a clock speed of up to 2.5GHz, compared to a 2GHz limit for the other processors.

The XLP II offers four-way multithreading, a four-issue superscalar engine, and out-of-order execution, using the same 64-bit MIPS EC4400 cores. NetLogic never talks about the number of cores, but rather speaks in terms of NXCPUs, which is its way of describing the SoCs' "highly independent" threads.

Since the XLP II offers up to 80 NXCPUs, we can deduce that it will be available in models that extend up to 20 cores. Whereas the 16-core, 64-NXCPU XLP864 delivers up to 80Gbps throughput, the XLP II will reach up to 100Gbps, says NetLogic.

Super clusters reach 160 cores, 640 threads

The processors are touted for their scalability, enabling the ganging together of XLP II SoCs in socket clusters of up to eight. This enables a "fully-coherent system" that can "achieve an unprecedented scalability of up to 640 NXCPUs," claims NetLogic. This eight-SoC, 160-core cluster offers up to 800Gbps combined throughput, claims the company.

The XLP-standard tri-level cache architecture has been expanded to over 32MB of fully coherent on-chip cache. The cache is said to integrate four channels of DDR3 memory controllers, delivering over 545Gbps of off-chip memory bandwidth, says NetLogic.

In a cluster of eight SoCs, this is said to represent over 260MB of on-chip cache. This clustered super-SoC offers a combined 32 DDR3 memory ports, yielding 4.4Tbps of DRAM access, claims the company.

A second-generation, high-speed Inter-chip Coherency Interface (ICI) enables full processor and memory coherency across all 640 NXCPUs, claims the company. Among other benefits, this is said to make it easier to adapt software to run in Symmetric Multi Processing (SMP) or Asymmetric Multi Processing (AMP) modes. As a result, customers can develop "highly scalable, highly differentiated equipment spanning entry-level multi-Gigabit to high-end Terabit systems," claims NetLogic.

The XLP II also features a third-generation high-speed Fast Messaging Network that can provide higher-bandwidth, lower-latency communications among the 640 NXCPUs. In addition, an advanced on-chip interconnect for the memory sub-system plus a wide range of high-speed physical-layer and logical-layer networking interfaces are said to be available. Other SoC features include "sophisticated power management technology," says the company.

Networking, security, and virtualization engines

The XLP II processor cores are said to include improvements in pre-fetch performance, branch mis-predict penalties, and cache access latencies. Meanwhile, fully-autonomous hardware processing and acceleration engines include:

CPU virtualization engines for full-virtualization and para-virtualization modes network acceleration engines for ingress/egress packet parsing and management packet ordering engines deep packet inspection engines for Layer 7 application processing, intrusion prevention, malware detection, and regular expression search acceleration security acceleration engines for encryption, decryption and authentication protocols compression/decompression engines TCP segmentation offload engines RAID-5/RAID-6 acceleration engines storage de-duplication acceleration engines IEEE 1588 hardware time stamping There was no word on operating system support for the XLP II. However, the XLP processors are supported with a new ELPB-NE Linux development platform from Enea that combines Enea's Eclipse-based Enea Linux PlatformBuilder framework and Timesys' LinuxLink configuration and build system.

Stated Ron Jankov, president and CEO at NetLogic Microsystems, "We believe our highly differentiated XLP II processor is a true game-changer that will give us a significant competitive advantage in the communications infrastructure market."

Stated Linley Gwennap, principal analyst at The Linley Group and editor-in-chief of the Microprocessor Report, "NetLogic Microsystems is moving aggressively to 28nm technology ahead of the competition. The XLP II multi-core processor will deliver a sizeable leap in performance compared with today's popular XLP products."

Availability

The first members of the XLP II processor family will be available in the first quarter of 2012, with additional members expected to sample in the first half of 2012. NetLogic Microsystems will be disclosing additional technical details of its XLP II multi-core processor family at the upcoming Linley Tech Processor Conference in October. More information should eventually appear on the XLP II at NetLogic's XLP page .